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Inverter

	Introduction Objective Manual Procedure Experiment Theory Quiz Reference

Objective

(a) To design transistor level schematic of an Inverter using

Complementary CMOS logic
Pseudo NMOS logic

(b)To find the effect of load capacitance on the rise time and fall time and hence delay of output waveform.

(c)To find the effect of W/L of transistors on the output waveform.

Cite this Simulator:

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