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Logic Gates
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1)Which of the following gate will result in larger pMOS transistor size? 
  
2)Which of the following is preferred for realizing pull down network (PDN)? 
  
3)Assuming an electron-hole mobility ratio 2, determine the size of the pMOS and nMOS transistors in 180nm technology for a static NOR gate with equal tpLH and tpHL values. 
  
4)Let A and B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay of the two series NMOS inputs A and B which one would you place near to the output?
  
5)Which of the following statement is NOT TRUE about the CMOS dynamic logic circuit design?
  

  


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