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Digital VLSI Design Virtual lab
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Registers
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Registers
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Theory
Self Evaluation
Procedure
Simulator
Assignment
Reference
Feedback
Video
1)
Which configuration of latches will result in a rising edge register?
negative latch followed by a positive latch
negative latch followed by a negative latch
positive latch followed by a positive latch
positive latch followed by a negative latch
2)
The hold time of the register is
the time output must be held stable after the rising edge of the clock
the time output must be held stable before the rising edge of the clock
the time input must be held stable after the rising edge of the clock
the time input must be held stable before the rising edge of the clock
3)
The set up time of a register is
the time after the rising edge of the clock that the input data must be valid
the time before the rising edge of the clock that the input data must be valid
the time after the rising edge of the clock that the output data must be valid
the time before the rising edge of the clock that the output data must be valid
4)
For the correct operation of a shift register, which of the following conditions are important? (a) Clock period > setup time + hold time, (b) Clock to output delay > hold time.
(a) only
(b) only
both (a) and (b)
neither of them matter
5)
For the proper operation of a sequential circuit, which of the following condition need to be satisfied?
T > clock_to_output_delay + logic_circuit_propagation_delay
T > clock-to-output-delay + logic-circuit-propagation_delay + set-up_time
T > clock-to-output-delay + logic_circuit_propagation_delay + hold_time
T > clock_to_output_delay + hold_time + set_up_time
Cite this Simulator:
vlab.amrita.edu,. (2011). Registers. Retrieved 3 May 2024, from vlab.amrita.edu/?sub=59&brch=165&sim=907&cnt=3
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