In this experiment a digital communication system employing BPSK is studied. Random data for transmission is generated and it is tranmitted using BPSK modulation. After passing the modulated signal over a band limited channel the data is demodulated using either

(a) Squaring loop or

(b) using a Costas loop

The different modules can be Remotely connected with the help of NI Switch (2529/2- wire 8 by 16 matrix).

Theory

Data Generation

The 2.7 MHz on- board oscillator (MCLK1) goes to the input of the Divider Logic block (MCLKx). This 2.7MHz frequency is used as the Master Clock for generating the data clock and consequently the final data i.e.‚output of the Pseudo Random Sequence Generator (PRBS). The Divider Logic derives ‘eight’possible data rates from MCLK1 by varying the select signals S2‚S1 and S0‚ and the data rates at the output of the Select Logic block can be set to one of these eight possible values by varying the jumper settings. The jumper in the PRBS sequence selector can be set to select ‘short sequence or long sequence’. But here in our experiment we have selected the short sequence and Select Logic as 1 1 1.

Figure2. Modulation and Up-converting Modulated data block diagram

Channel Isolation and Down-conversion

The 10.7 MHz BPF1 BPSK output signal is then fed into the ‘signal input’f the TX Channel Isolation board. A 1 meter ‘black’ coaxial cable(provided with the system) is connected from the TX Channel Isolation board to the RX Channel Isolaion board.The BPSK modulated signal now passses from the transmitter to the receiver through the coaxial cable communication medium.The output of the RX Channel Isolation goes to the 10.7 MHz input of the Mixer block on the Receiver Trainer. There is an Add-on-Oscillator Module which provides the Lo_Down frequency of 10.495 MHz. In order to demodulate this downconverted signal, its output is connected to the Lo_Down input of Mixer block.Thus the receiver first downconverts the 10.7 MHz signal to the lower frequency using Lo_Down of 10.495 MHz .

Figure3. Channel Isolation and Down-conversion block diagram

Demodulation

The downconverted output is then passed through a band-pass filter and then buffered and hard-limited to a TTL signal and is further fed to the digital Squaring loop or Costas loop as per requirement for Demodulation and Carrier recovery.

Carrier Recovery

The two common methods for BPSK carrier recovery are: (1) Squaring the BPSK signal then dividing by two and (2) the 180° Costas loop. The first technique relies on the fact that, because the BPSK modulation causes ±180° phase transitions, its second harmonic will be phase-modulated by an ambiguous ±360°. The second harmonic is an unmodulated carrier at twice the frequency. Dividing this second harmonic of the carrier by two will result in a theoretically phase-coherent carrier. The advantage of the squaring-then divide circuit is that it is mathematically simple to analyze. However, in practice, controlling the phase offset will be somewhat complicated and layout dependent, the recovered carrier takes a different path from the demodulator path, and this creates a time differential that will result in a phase error. Also, several filters are required, making it difficult to maintain proper phase over the range operating frequencies. While the first method is a feed-forward technique, the Costas loop relies on feedback concepts related to the PLL. The Costas loop offers an inherent ability to self-correct the phase (and frequency) of the recovered carrier and, in the end, its implementation is no more complicated than the first technique. Its main disadvantage is involvement of a loop settling time.

 A Costas loop is a phased-locked loop used for carrier phase recovery from suppressed-carrier modulation signals, such as from double-sideband suppressed carrier signals. It was invented by John P. Costas at General Electric in the 1950s. Its invention was described as having had "a profound effect on modern digital communications". The primary application of Costas loops is in wireless receivers. Its advantage over the PLL-based detectors is that at small deviations the Costas loop error voltage is sin (2(θ_i−θ_f)) vs sin(θ_i−θ_f). This translates to double the sensitivity and also makes the Costas loop uniquely suited for tracking  doppler-shifted carriers esp. in OFDM and GPS receivers

In the usual implementation of a Costas loop, a local voltage-controlled oscillator provides quadrature outputs, one to each of two phase detectors, e.g., product detectors. The same phase of the input signal is also applied to both phase detectors and the output of each phase detector is passed through a low-pass filter. The outputs of these low-pass filters are inputs to another phase detector, the output of which passes through noise-reduction filter before being used to control the voltage-controlled oscillator. The overall loop response is controlled by the two individual low-pass filters that precede the third phase detector while the third low-pass filter serves a trivial role in terms of gain and phase margin.