The aim of this experiment is to design and plot the static (VTC) and dynamic characteristics of a digital CMOS inverter.

 

 

Introduction

 

The inverter is universally accepted as the most basic logic gate doing a Boolean operation on a single input variable. Fig.1 depicts the symbol, truth table and a general structure of a CMOS inverter. As shown, the simple structure consists of a combination of an pMOS transistor at the top and a nMOS transistor at the bottom.

 

Fig.1: Symbol, circuit structure and truth table of a CMOS inverter

 

CMOS is also sometimes referred to as complementary-symmetry metal–oxide–semiconductor. The words "complementary-symmetry" refer to the fact that the typical digital design style with CMOS uses complementary and symmetrical pairs of p-type and n-type metal oxide semiconductor field effect transistors (MOSFETs) for logic functions. Two important characteristics of CMOS devices are high noise immunity and low static power consumption. Significant power is only drawn while the transistors in the CMOS device are switching between on and off states. Consequently, CMOS devices do not produce as much waste heat as other forms of logic, for example transistor-transistor logic (TTL) or NMOS logic, which uses all n-channel devices without p-channel devices.

 

 

Inverter Static Characteristics (VTC)

 

Digital inverter quality is often measured using the Voltage Transfer Curve (VTC), which is a plot of input vs. output voltage. From such a graph, device parameters including noise tolerance, gain, and operating logic-levels can be obtained.

Fig.2: Voltage Transfer Curve for a typical 20 μm Inverter

 

Ideally, the voltage transfer curve (VTC) appears as an inverted step-function - this would indicate precise switching between on and off - but in real devices, a gradual transition region exists. The VTC indicates that for low input voltage, the circuit outputs high voltage; for high input, the output tapers off towards 0 volts. The slope of this transition region is a measure of quality - steep (close to -Infinity) slopes yield precise switching. The tolerance to noise can be measured by comparing the minimum input to the maximum output for each region of operation (on / off). This is more explicitly shown in the fig.3.

Fig.3: Definition of noise margin

 

Noise margin : is a parameter intimately related to the transfer characteristics. It allows one to estimate the allowable noise voltage on the input of a gate so that the output will not be affected. Noise margin (also called noise immunity) is specified in terms of two parameters - the low noise margin N_L, and the high noise margin N_H . Referring to above figure, N_L is defined as the difference in magnitude between the maximum LOW input voltage recognized by the driven gate and the maximum LOW output voltage of the driving gate. That is, N_L =|V_IL - V_OL|. Similarly, the value of N_H is the difference in magnitude between the minimum HIGH output voltage of the driving gate and the minimum HIGH input voltage recognizable by the driven gate. That is, NM_H =|V_OH - V_IH|. Where V_IH: minimum HIGH input voltage, V_IL: maximum LOW input voltage, V_OH: minimum HIGH output voltage, V_OL: maximum LOW output voltage.

 

Inverter Dynamic Characteristics

 

 

Fig.4 shows the dynamic characteristics of a CMOS inverter. The following are some formal definitions of temporal parameters of digital circuits. All percentages are of the steady state values. 

Fig.4: Dynamic characteristics of CMOS inverter

 

Rise Time (t_r) : Time taken to rise from 10% to 90%. 

Fall Time (t_f): Time taken to fall from 90% to 10%.

Edge Rate (t_rf): (t_r + t_f )/2. 

High-to-Low propagation delay (t_pHL): Time taken to fall from V_OH to 50%.

Low-to-High propagation delay (t_pLH): Time taken to rise from 50% to V_OL. 

Propagation Delay (t_p): (t_pHL + t_pLH)/2. 

Contamination Delay (t_cd): Minimum time from the input crossing 50% to the output crossing 50%.