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Digital VLSI Design Virtual lab
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4x1 Multiplexer
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4x1 Multiplexer
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Theory
Self evaluation
Procedure
Simulator
Assignment
Reference
Feedback
Video
1)
Which of the following is the correct output expression for an 4x1 MUX? [Given D0, D1, D2, D3 are the data inputs and S0, S1 are the select inputs].
Y = D0*D1*S0 + D2*D3*S1
Y = D0*S1'*S0' + D1*S1'*S0 + D2*S1*S0' + D3*S1*S0
Y = D0*S0' + D1*S1' + D2*S0 + D3*S1
Y = D0*D1*S0 + D2*D3*S1 + D0'*D1'*S0 + D2'*D3'*S1
2)
Which of the following is NOT TRUE about a multiplexer?
For a 2^n input MUX, there are n output lines
MUX is a combinational circuit
MUX can be implemented using three-state gates
Apart from input and output lines, it has selection lines also
3)
To implement an 8x1 MUX using 2x1 MUXs alone, we require ____ number of them.
4
6
7
8
4)
The advantage of using transmission gate logic over pass transistor logic is
The number of transistors is reduced
The primary inputs only drive the gate terminals of the MOSFET
It gives a solution to the voltage-drop problem
They have no associated series resistances
5)
In a MUX based on nMOS pass transistor logic, the maximum output voltage obtained is
Vdd
Vdd-Vtn
Vdd-2*Vtn
Vdd/2
Cite this Simulator:
vlab.amrita.edu,. (2011). 4x1 Multiplexer. Retrieved 29 April 2024, from vlab.amrita.edu/?sub=59&brch=165&sim=904&cnt=1689
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